0. old, still waiting for ack

1. For the upcoming release ===============================================================================
- RELEASE: enable polybool2 for dev, disable polybool2 by default before the release
- RELEASE: polybool2: at the end of the full rewrite, remove /local/pcb/want_polybool and PCB_WANT_POLYBOOL (from scconfig and config.h too!)
- FEATURE: DRC: silk over mask opening or paste (easy, stock) [report: Igor2, Vuokko]
- FEATURE: add the top/bottom courtyard layers to default*.lht
- BUG: changing drc_query definitions from the GUI doesn't mark the board changed even tho these are always saved with the board [report: Jared]
	- new board, draw, save
	- {i c p}, navigate to drc_query
	- go to the definitions tab, change min_drill's value to 30mil
	- close everything and quit -> no "OK to lose data?" dialog at the end
- BUG: preferences dialog on project role overwrites project.lht, removing sch-rnd's or other any other app's subtrees [report: Jared]
	- create non-empty project file (copy one with sch-rnd stuff)
	- create A.rp in same dir, save, load
	- {i c p}, set project role, change backup timer on first tab
	-> observe project.lht overwritten, sch-rnd subtree removed
- FEATURE: PCBWay wants lines of the BoM numbered; need an auto-increment ("row number") subst in the template [report: Jared]

2. For later releases ===============================================================================
- FEATURE: footprint versioning: http://repo.hu/cgi-bin/pool.cgi?project=pcb-rnd&cmd=show&node=footprint_ver
- librnd 4.3: search for TODO("librnd 4.3.0
- FEATURE: shift-click subc replace or reimport subc-replace: attempt to preserve floater positions and per terminal clearances and thermals [report: aron]
- DOC: pool node on how to use pixmap for breadboading
- BUG: bug_files/TODO/ppc_full.*: poly-clear-poly should respect full-poly flag and apply all islands only if full-poly is set
- CLEANUP: rewrite query's parent_net_len_found_cb() to collect objects in a tree (from->to objects, at most 2 'to' objects from a single 'from'); use slab allocation for tree elems; see bug_files/revp.lht: {n l o} on the long horizontal line causes zig-zagging map that a single segment reverse won't fix; also revise pads ascii write with this [report: cuvoodoo]
- CLEANUP: TODO27: undo's removed list shouldn't depend on object IDs but probably remove list index because IDs are not unique if we want our operations to retrain IDs. Repro: shift-click subc replace twice, then undo; or drag&drop move selected object and undo [report: Igor2]
- BUG: Lihata persistent save:
	- flag compatibility: save unknown, string-flags as loaded by io_pcb
	- ind: FONTS: second font indents incorrectly
	- ind: indentation bug in inline struct therm: closing } is preceded by indentation whitespace for some reason
	- keep numeric format: test all
	- keep unknown subtrees
	- BUG: lhtpers indentation: bug_files/lhtpers_ins/; breakpoint in pers_table.c:34 and debug why the newline is getting in [report: Igor2]
- rubber band stretch routing:
	- IGNORE: BUG: Rubberband move line endpoints ignores connected arc endpoints. [Fixing:Ade]
	- remove auto_via from the conf and code
- librnd later:
	- FEATURE: librnd API: library window: allow long tags and long location text to split: rich text widget in librnd [report: Igor2]
- BUG: orcad netlist importer can't handle parametric footprints, see bug_files/TODO/orcad.net

3. Long term ===============================================================================
- FEATURE: rbs_routing extras
	- move via, stretch attached nets
	- move multiple vias/pins/pads, stretch attached nets
	- net autocompletion in sequential routing
	- seq routing: cut existing segment and re-route
- FEATURE: multi: merge sch-rnd r4718 for proper multiboard support later
- BUG: I/O bugs:
	- eagle:
		- BUG: xml: eagle XML import fails on polygon import reported by miloh, test file pcb-rnd-aux poly_selfi/eagle_polygon_crash.brd [report: erich], due to input file containing an invalid polygon: a self intersecting poly in line 156 - consider handling "width"?
		- bin: eagle binary format v3 and libraries do not have a DRC block specifying restring or minimum feature widths. Binary loader should add a DRC block in these cases to the tree with the minimum settings needed for padstacks and features to load sensibly. [erich].
		- bin: padstack clearances for element pins will rely on connectivity to other polygons layer by layer defined in the netlist; test case: alien_fmt_test/io_eagle_bin/net_poly_conn
- CLEANUP: revise dialog boxes for string/integer input box character length
- CLEANUP: think over how to handle subc selection: selecting all parts automatically is bad for propedit; bug_files/subcsel.bug [report: Wojciech]
	- BUG: propedit adding/deleting attributes inconsistency; search depth problem (see TODO#28)  bug_files/subcsel.bug [report: Ade]
	- BUG: select a subc, propedit selection: padstacks are counted twice (e.g. for lid/thermal) [report: gpaubert]
- CLEANUP: footprint lib rework
	- fooprint upgrade know-how, document these:
		- if there's a pcb-rnd::fpline attribute, that's the footprint line to search in the lib (this is the case for pcb-rnd from r40066 for manually loaded footprints)
		- otherwise use the footprint attribute (this is the case for sch imported footprints)
		- pre-r40066 manually placed footprints won't be able to upgrade cleanly (but this problem is gone after the first manual upgrade)
	- BUG: bug_files/TODO/TO247.rp, { w l }, select TO247, shift click onto subc in TO247.rp layout: 90 degree error [report: Erich]
		-> wrong subc-aux x and y lines (names mixed up)
		-> apply patch in bug_files/fp_rework to fix that
		- check with script util/devhelper/subc-aux-verify
		- sot23 and the whole sot* series is affected as well
	- revise silk graphics for at least smd
	- add assy drawing
	- add keepout
	- revise pad sizes and hole sizes, maybe starting from bedrock
	- revise 3d (openscad) models if they still line up
	- redesign pwrjack to have slots instead of large holes
	- parametric common bugs:
		- so(8,pad_clearance=0.1mm) creates pad clearance twice as large as needed [report: aron]
- BUG: start new layout: pcb-rnd foo.rp, export scad model, will export to foo.scad by default; then start new layout, save layout as bar.rp. When using export dialogue, dialogue defaults to previous filename foo.XXX for any of the export options. [report: Erich]
- BUG?: enforce style clearance doesn't work with middle-line rubber band move, see bug_files/TODO/drag.rs [report: Majenko]
	-> may be a non-bug, if we take this as a line move operation (doesn't enforce)
- FEATURE: emsim-rnd (dcpower)
- FEATURE: DRC: custom DRC ignores [report: bdale 2025-02-12 IRC]
	- a large table of:
		- obj ID (vs. obj ID or list of objs that all need to present in the DRC report)
		- DRC error class
		- what to do with it ("ignore" for now)
		- user specified comment (reason)
	- maybe save this in the config, design role
- FEATURE: DRC: minimum mask bridge width check [report: John Wehle, Igor2]
	- need to use find.c to get "nets" of mask objects (including padstacks)
	- then use the normal bloat-intersect code to see if two of them are closer than the required value
	- BUG: polybool2: pcb-rnd/work/test_poly/phatch.lht: maybe {m d t} and PolyHatch(0, c) -> poly offseting bug on sharp corners ml=4159 [report: Majenko]
		-> simpler test: PolyOffs(-10mil) also breaks
		-> polybool2 bug: autotest2/offset03
		-> solution:
			-> write and expose a function that works on polyarea instead of pline because of offset04 where a single pline would end up as two islands
			-> use pline_dup_with_offset_corner()
			-> then do a new self isc resolver that trusts input edge directions and removes loops with negative direction (unless we are doing holes!)
		-> revise the original offset calls in pcb-rnd and decide where to use the new one
		-> consider rnd_pline_dup_offset() to start with: if (offs < 0) return pline_dup_with_offset_corner(src, offs, RND_PLINE_CORNER_SHARP); (also move #include offset2.c to the top of the file for this)
- FEATURE: "thermal recipe" so a padstack thermal can be put in a padstack or subc and it is changed with the layer binding [report: jg]
- FEATURE: netlist2: bug_files/ratside.txt optional rats constraints [report: Vuokko]
- FEATURE: openems mesher: do not ignore padstack copper [report: Evan]
- FEATURE: netlist import's ElementList(): [report: aron]
	- postpone actions, present a list of changes only to the user (GUI)
	- each item of the list should contain the corresponding actions to make the change
	- the user can execute these items one by one
- CLEANUP: move pcb_pixmaps into the board struct, board free should free it, and it should call rnd_render->pixmap_free()
- CLEANUP: padstack bbox:
	- per layer: keep a bbox per transformed shape per prototype, then getting the bbox of a padstack ref on a specific layer is looking up the shape, then 4 integer additions [report: Wojciech]
	- when calculating overall padstack bbox, ignore layers that are not present? but then a layer change would require a recalc (but this is true for subcs too!) [report: Wojciech]
- FEATURE: depth controlled mech layers (routed) for internal cavities: http://www.saturnelectronics.com/products_capabilities/internal-cavity_boards.html -> user script, similar to on_every_layer: convert lines into bbvia slot padstacks; only when we already export bbvia in excellon; alternative: layer attribute on mech layers
- FEATURE: XOR rendering upgrade:
		- experiment with 'emboss' kind of drawing instead of xor so rendering can stay 'direct'
		- if worked: allow padstack xor draw to draw all shapes on all layers
- CLEANUP: layer group rewrite: remove PCB_MAX_LAYERGRP and PCB_MAX_LAYER and make them dynamic - use libualloc stack with reasonable page size and local var first page
	- make pcb_layervis_save_stack() reentrant by letting the caller allocate the save buffer
- CLEANUP: reduce: get rid of autorouter/vector.[ch]
- FEATURE: footprint selector for sch-rnd
	- command line option (or action script + shell wrapper) to start up with the library window only
	- persist; stdio interface with sch-rnd being able query currently selected footprint
	- problem: it is impossible to hide the top window in a portable way
		-> maybe finish docking first and dock the library window in the main window
		-> then hide every other dock, menu and drawing area in the main window

4. Low prio ===============================================================================
- BUG: elliptic: gtk2_gl: RTT/arc_sizes.lht - elliptical arc corner case render bug [report: Wed]
- BUG: elliptic: RTT/arc_sizes.lht - unable to move arcs which have different width and height [report: Ade] - rewrite pcb_is_point_on_arc() elliptical case at the bottom
- BUG: if foo() v0 exists in ~/.pcb-rnd/footprint and foo() v1 exists in ~/pcblib the tree view in the left paane of {w l} will load foo() v0 in ~/.pcb-rnd even if foo() v1 under ~/pcblib is being selected in the GUI with a mouse click. GUI selection fail.  [report: Erich] 
- CLEANUP/BUG: undo operation while drawing a multiple segment line doesn't change segment attached to the crosshair [report:wojciechk8]
	- tool_line.c depends on pcb_undo()'s return value; can be fixed only when the old undo system is removed
- CLEANUP: layer order from data
	- build a list of layers rendered, in the order of rendering while drawing layer groups; maybe use gdl and move the group to the end and use a terminator item;  get pcb_search_obj_by_location_() to use this list for ordering
	- BUG?: Far-side silk text can be selected and moved when the mouse is over front-side subcircuit. (but this is what we had with elements too! -> rewrite search.c to be a 'script' config) bug_files/TODO/farsilk.lht [report: Ade]
- FEATURE: DRC should warn for thin poly hair
- FEATURE: scconfig: menuconfig and a config file for scconfig: requires a more declarative dependency handling system -> being done in scconfig2
- FEATURE: alien file format: IDF (for 3D cads; spec comes with free permissive license; freecad should import it; ml: geda-user 18921; work/alien_formats/IDF; OP not interested)
